The present invention relates to computer-aided design techniques and, more particularly, to the design of integrated circuitry using hardware description languages.
Hardware description languages, such as VHDL (Very High Speed Integrated Circuit Hardware Description Language), are widely used for the design, documentation, and simulation of integrated electronic circuitry. VHDL, for example, offers three different modes for the characterization of a complex integrated circuit: structural, data flow, and behavioral descriptions. The 1993 version of VHDL is described in IEEE Standard VHDL Language Reference Manual, IEEE Std. 1076-1993. The VHDL structural description mode focuses on the arrangement of interconnected hardware components, or xe2x80x9cblocks,xe2x80x9d defined by type and interface. The VHDL data flow description mode breaks down the circuit design into a set of register assignments that take place under the control of specified gating signals. The VHDL behavioral description mode defines the design in terms of a series of sequential process statements that resemble a high-level programming language. Although a design can be characterized by a collection of structural, data flow, and behavioral descriptions, the behavioral description mode will be described in greater detail herein.
In the VHDL behavioral description mode, the designer codes a set of process statements that characterize the function, or xe2x80x9cbehavior,xe2x80x9d of a particular block. The process statements execute concurrently, whereas functions set forth within the process statements execute sequentially. Process statements are used to model the behavior of a variety of components such as registers or multiplexers. Each process statement includes a sensitivity list that identifies one or more signals to which the process statement is sensitive. In other words, the sensitivity list specifies particular signals that trigger the behavior defined by the process statement. The process statement only executes in response to a change in the status of one of the signals in the sensitivity list, or in response to a synchronous clocking signal identified in the sensitivity list. In either case, in response to the signal, the process statement executes the associated functions to carry out one or more register transfer operations. Each register transfer operation, in turn, affects the condition of another signal, leading to the execution of other process statements having sensitivity lists that incorporate the affected signal.
The human designer generally is required to manually enter the sensitivity list at the beginning of a process statement. Unfortunately, process statements and associated sensitivity lists can be difficult to generate and maintain. As a design evolves, for example, the content of a sensitivity list and the functions implemented by a process statement are subject to constant change. Moreover, the changes occur within an extremely complex design having potentially hundreds of process statements and sensitivity lists. Consequently, maintenance of the sensitivity lists presents a significant challenge. If a sensitivity list is incorrect, the overall design or portions thereof may fail to simulate correctly. In particular, when the sensitivity list omits the necessary triggering signals, the associated process statement will not execute in response to appropriate signal changes. Instead, the process statement effectively will lie dormant despite changes in signals to which the process statement is intended to respond. Lack of sensitivity list integrity compromises the function of the overall design and causes incorrect simulation.
Identification of the source of the problem, i.e., a defective sensitivity list, is a painstaking manual process that can take hours and, in many cases, days. This manual debugging effort can result in substantial delays and drains resources from the design effort, significantly increasing the design cycle and time to market. In the end, sensitivity list debugging is a costly nuisance that is difficult to avoid due to design complexity and the prevalence of human error.
The present invention is directed to a method for analyzing the integrity of a sensitivity list for a process statement in a hardware description language file. The present invention also is directed to a computer readable medium encoded with a computer program arranged to execute such a method. An example of a hardware description language to which the method can be applied is VHDL.
The method compares an actual sensitivity list from a behavioral process statement in a hardware description language file to an expected sensitivity list that includes one or more parameters expected to appear in the actual sensitivity list. In the event the actual sensitivity list deviates from the expected sensitivity list, the integrity of the actual sensitivity lists can be compromised. In this case, an advisory can be generated to identify the deviation and, if desired, note its location within the hardware description language file. In this manner, the designer can quickly find the defective sensitivity list and correct it prior to simulation.
A method configured according to the present invention can significantly reduce the time and effort involved in sensitivity list debugging. Consequently, the designer can devote more time and resources to the design effort and the end objective of producing the subject integrated circuit. In many cases, reduction of debugging costs will bear significantly on the final cost of the design. At the same time, reduction of debugging time can shorten the design cycle. Moreover, such a method can simply alleviate the considerable distraction and nuisance incurred by the designer as a result of sensitivity list errors.
The present invention, in one embodiment, provides a method for analyzing a sensitivity list in a hardware description language file, the method comprising selecting an actual sensitivity list from a hardware description language file, the actual sensitivity list including one or more parameters that trigger a process statement, generating an expected sensitivity list including one or more parameters expected to appear in the actual sensitivity list, comparing the actual sensitivity list to the expected sensitivity list, and generating an advisory in the event the actual sensitivity list deviates from the expected sensitivity list.
In another embodiment, the present invention provides a computer readable medium encoded with a computer program, the program being arranged such that, when the program is executed, a computer performs the acts of selecting an actual sensitivity list from a hardware description language file, the actual sensitivity list including one or more parameters that trigger a process statement, generating an expected sensitivity list including one or more parameters expected to appear in the actual sensitivity list, comparing the actual sensitivity list to the expected sensitivity list, and generating an advisory in the event the actual sensitivity list deviates from the expected sensitivity list.
In a further embodiment, the present invention provides a method for analyzing a sensitivity list for a process statement in a hardware description language file, the method comprising accessing a hardware description language file, the hardware description language file including process statements, wherein each of the process statements includes an actual sensitivity list containing one or more signals that trigger the respective process statement, selecting one of the process statements, generating an expected sensitivity list for the selected process statement, the expected sensitivity list containing one or more names including names of signals expected to trigger the selected process statement, verifying whether one or more of the names in the expected sensitivity list is present in the actual sensitivity list for the selected process statement, and generating an advisory in the event one or more of the names in the expected sensitivity list is absent from the actual sensitivity list.
In an added embodiment, the present invention provides a computer readable medium encoded with a computer program, the program being arranged such that, when the program is executed, a computer performs the acts of accessing a hardware description language file, the hardware description language file including process statements, wherein each of the process statements includes an actual sensitivity list containing one or more signals that trigger the respective process statement, selecting one of the process statements, generating an expected sensitivity list for the selected process statement, the expected sensitivity list containing one or more names including names of signals expected to trigger the selected process statement, verifying whether one or more of the names in the expected sensitivity list is present in the actual sensitivity list for the selected process statement, and generating an advisory in the event one or more of the names in the expected sensitivity list is absent from the actual sensitivity list.
In another embodiment, the present invention provides a method for generating an expected sensitivity list for a process statement in a hardware description language file, the method comprising accessing a hardware description language file, the hardware description language file including process statements, selecting one of the process statements, scanning an argument section of the selected process statement, extracting names of signals from the argument section, and generating an expected sensitivity list for the selected process statement, the expected sensitivity list containing the extracted names.
In an additional embodiment, the present invention provides a computer readable medium encoded with a computer program, the program being arranged such that, when the program is executed, a computer performs the acts of accessing a hardware description language file, the hardware description language file including process statements, selecting one of the process statements, scanning an argument section of the selected process statement, extracting names of signals from the argument section, and generating an expected sensitivity list for the selected process statement, the expected sensitivity list containing the extracted names.